1
Data sheet acquired from Harris Semiconductor
SCHS205A
Features
Typical Propagation Delay: 6ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
High-to-Low Voltage Level Converter for up to V
l
= 16V
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . 55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30%of V
CC
at
V
CC
= 5V
Description
The CD74HC4049 and CD74HC4050 are fabricated with
high-speed silicon gate technology. They have a modified
input protection structure that enables these parts to be
used as logic level translators which convert high-level logic
to a low-level logic while operating off the low-level logic
supply. For example, 15-V input pulse levels can be down-
converted to 0-V to 5-V logic levels. The modified input
protection structure protects the input from negative
electrostatic discharge. These parts also can be used as
simple buffers or inverters without level translation. The
CD74HC4049 and CD74HC4050 are enhanced versions of
equivalent CMOS types.
Pinout
CD74HC4049, CD74HC4050
(PDIP, SOIC, TSSOP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG.
NO.
CD74HC4049E
55 to 125
16 Ld PDIP
E16.3
CD74HC4050E
55 to 125
16 Ld PDIP
E16.3
CD74HC4049M
55 to 125
16 Ld SOIC
M16.15
CD74HC4050M
55 to 125
16 Ld SOIC
M16.15
CD74HC4050PW
55 to 125
16 Ld TSSOP
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
the M suffix or the R suffix to the PW package to obtain the
variant in the tape and reel.
2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or
customer service for ordering information.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
V
CC
1Y
1A
2Y
2A
3Y
GND
3A
NC
6A
NC
5Y
5A
4Y
4A
6Y
4049
4050
4050
4049
V
CC
1Y
1A
2Y
2A
3Y
GND
3A
NC
6A
NC
5Y
5A
4Y
4A
6Y
February 1998 - Revised June 1999
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
1999 Texas Instruments Incorporated
CD74HC4049,
CD74HC4050
High-Speed CMOS Logic
Hex Buffers, Inverting and Non-Inverting
[ /Title
(CD74H
C4049,
CD74H
C4050)
/Sub-
ject
(High
Speed
CMOS
Logic
Hex
2
Functional Diagram
1A
1Y
2Y
3A
3Y
GND
1
2
3
4
5
6
16
14
13
12
NC
5A
4Y
5Y
6A
NC
11
9
7
10
4A
2A
V
CC
8
15
6Y
4050
4049
4049
4050
1Y
2Y
3Y
6Y
NC
5Y
Logic Diagrams
HC4049
HC4050
A
Y
A
Y
CD74HC4049, CD74HC4050
3
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . 0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< 0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . .
20mA
DC Output Diode Current, I
OK
For V
O
< 0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> 0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .
25mA
DC V
CC
or Ground Current, I
CC or
I
GND
. . . . . . . . . . . . . . . . . .
50mA
Operating Conditions
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . .55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3)
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
149
Maximum Junction Temperature (Hermetic Package or Die) . . . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . 65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3.
JA
is measured with the component mounted on an evaluation PC board in free air.
V
CC
V
l
+7V
+16V
VOLTAGE
RELATIONSHIPS
MAXIMUM LIMITS
DC Electrical Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
40
o
C TO 85
o
C
55
o
C TO
125
o
C
UNITS
V
I
(V)
I
O
(mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
Low Level Input
Voltage
V
IL
-
-
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
High Level Output
Voltage
CMOS Loads
V
OH
V
IH
or V
IL
0.02
2
1.9
-
-
1.9
-
1.9
-
V
0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
0.02
6
5.9
-
-
5.9
-
5.9
-
V
High Level Output
Voltage
TTL Loads
4
4.5
3.98
-
-
3.84
-
3.7
-
V
5.2
6
5.48
-
-
5.34
-
5.2
-
V
Low Level Output
Voltage
CMOS Loads
V
OL
V
IH
or V
IL
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
Low Level Output
Voltage
TTL Loads
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
Input Leakage
Current
I
I
V
CC
or
GND
-
6
-
-
0.1
-
1
-
1
A
15
-
6
-
-
0.5
-
5
-
5
Quiescent Device
Current
I
CC
V
CC
or
GND
0
6
-
-
2
-
20
-
40
A
NOTE: For dual-supply systems theorectical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
CD74HC4049, CD74HC4050
4
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
40
o
C TO
85
o
C
55
o
C TO
125
o
C
UNITS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
Propagation Delay,
nA to nY HC4049
nA to nY HC4050
t
PLH,
t
PHL
C
L
= 50pF
2
-
-
85
-
105
-
130
ns
4.5
-
-
17
-
21
-
26
ns
6
-
-
14
-
18
-
22
ns
C
L
= 15pF
5
-
6
-
-
-
-
-
ns
Transition Times (Figure 1)
t
TLH
, t
THL
C
L
= 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
Input Capacitance
C
I
-
-
-
-
10
-
10
-
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
-
5
-
35
-
-
-
-
-
pF
NOTES:
4. C
PD
is used to determine the dynamic power consumption, per gate.
5. P
D
= V
CC
2
f
i
(C
PD
+ C
L
) where f
i
= Input Frequency, C
L
= Output Load Capacitance, V
CC
= Supply Voltage.
Test Circuit and Waveform
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
t
r
= 6ns
t
f
= 6ns
90%
CD74HC4049, CD74HC4050
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright
1999, Texas Instruments Incorporated
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